Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device in which a plurality (e.g., three) layers of materials having different work functions are stacked.
Semiconductor devices are designed for predetermined purposes by implanting impurities or depositing new materials at predetermined regions in a silicon wafer. Semiconductor memory devices include a number of elements to carry out given purposes, for example, transistors, capacitors, resistors, and the like. Individual elements are interconnected through a conductive layer so that data or signals are communicated therebetween.
As technologies for manufacturing semiconductor devices develop, intensive research has been conducted on methods for forming more chips on a single wafer by increasing the integration degree of semiconductor devices. In order to increase the integration degree of semiconductor devices, the minimum feature size required for the design rules of the devices becomes smaller.
For example, the distance between a bit line and a gate is gradually reduced in proportion to the increasing degree of integration. However, as a result, parasitic capacitance between the bit line and the gate is also increased. In order to obviate the above problem, a buried gate structure in which a gate is buried in a semiconductor substrate has recently been proposed and developed.